The importance of the chip is self -evident. Needless to say, everyone is very clear. If the chip, mobile phones, computers, robots, electrical appliances and other electronic products will not be able to run!
DIP
DIP is a form of packaging in the 1970s. It can meet the requirements of most integrated circuits at that time. The manufacturing cost is low and it is easier to achieve automation of packaging automation printing testing. Therefore, it has a leading position in the integrated circuit packaging for a considerable period of time. However, DIP's pin spacing is large (2.54mm) and occupy more space with PCB boards. For this reason, improvement forms such as SHDIP and SKDIP have appeared. It is less improved, but it is difficult to increase the DIP maximum pin (the maximum pins is 64) and adopt a pore insertion method, which has greatly limited its application.
PGA
In order to break through the limit of pins, PGA packaging was developed in the 1980s. Although its pin spacing is still maintained at 2.54mm or 1.77mm, due to the use of the bottom surface, the number of pins can be as high as 500 ~ 600 600. strip.
SOP
With the emergence of surface installation technology (SMT), the number of DIP packaging gradually decreases, surface installation technology can save space, improve performance, and can be placed on the upper and lower sides of the printing circuit board. SOP came into being. Its pins were led from both sides, and it was flat packaging. The pin could be directly welded on the PCB board and no longer needed sockets. Its pins are also reduced from 2.54 mm of DIP to 1.77mm. Later, SSOP and TSOP improved, but the number of pins was still limited.
QFP
QFP is also flat packaging, but their pins are led from the four sides, and they are horizontal straight lines. They have a small inductance and can work at a higher frequency. The pins are further reduced to 1.00mm, even 0.65mm and 0.5mm, and the number of pins can reach 500, so this packaging form is widely welcomed. However, when the number of foot tube is not high, SOP and its deformation SOJ (J -type pins) are still preferred packaging forms, and it is also the most encapsulated form currently produced.
Square flat package-QFP (QUAD FLAT PACKAGE)
[Features] Small pins and thin spacing are often used in large -scale or large -scale integrated circuits. SMT (surface installation technology) must be used for welding. Easy to operate and high reliability. The ratio of the chip area to the packaging area is large.
Small frame package-sop (Small Outline Package)
[Features] It is suitable for SMT installation wiring, parasitic parameters are reduced, high -frequency applications, high reliability. The pin is far from the chip, the finished product rate increases and the cost is lower. The ratio of the chip area to the packaging area is about 1: 8
Small-sized J-type pin packaging-soj (Smal Outline J-Lead)
There is a lead chip carrier-LCC (Leaded Chip Carrier)
According to statistics in 1998, DIP accounts for 15%of the total packaging, 57%of SOPs in total packaging, and QFP account for 12%. It is expected that the share of DIP will further decrease in the future, and SOP will decline, and QFP will maintain the original share, and the sum of the three will still account for 80%of the total packaging volume.
The above three forms of packaging are divided into plastic packaging and ceramic bags. Plastic packaging is made of perioprexic resin after the lead key is combined. The moisture resistance of epoxy resin is good and the cost is low, so it has a dominant position in the above packaging. Ceramics packaging has the characteristics of high gas tightness, but the cost is high. When there are high requirements for heat dissipation performance and electrical characteristics, or for national defense military needs, ceramic packaging is often used.
PLCC
PLCC is a piece of chip carrier packaging with plastic pins (actually J-shaped pins) (also known as four-sided flat J-shaped foot packaging QFJ (QUAD FLAT J-Lead Package)), so it uses chip carrier because of sometimes because of chip carriers In the system, the integrated circuit needs to be replaced, so the chip is encapsulated in a carrier, and then the carrier is inserted into the socket. In this way, as long as the loader is taken on the socket, another carrier can be easily replaced.
LCC
LCC calls the ceramics without a cable carrier packaging (there is actually a pin but not extended. It is turned on the four sides of the ceramic tube shell through contact). Sometimes it is also called CLCC, but usually not adds C. In the case of ceramic packaging. If the structure and pin shape of the carrier change slightly, the pins of the carrier can be welded directly with the PCB board without the need for sockets. This packaging is called LDCC, that is, ceramic has a pins -type carrier packaging.
Qfn
QFN is the name stipulated by the Japanese Electronic Machinery Industry Association. The enclosure is equipped with an electrode contact. Because there is no pitch, the stickers are smaller than QFP and the height is lower than QFP. However, when the printed substrate and the package are generated, it cannot be relieved at the electrode contact. Therefore, the electrode contact is difficult to achieve the pins of QFP, generally about 14 to 100. There are two types of materials: ceramics and plastic. When there are LCC marks, they are basically ceramic QFN. The center of the electrode contact is 1.27mm. Plastic QFN is a low -cost packaging of glass epoxy resin printing substrate substrate.
BGA ball racket package package
When the frequency of IC exceeds 100MHz, the traditional packaging method may produce the so -called "Cross Talk" phenomenon, and when the number of ICs' pipes is greater than 208 PIN, the traditional packaging method is difficult.
Chip size package CSP
CSP (Chip Size Package) is a new packaging technology developed in recent years. It reduces the size of the chip encapsulation shape, and how big the size of the nude chip is and how big the packaging size is. The definition of CSP is: 1.2 times that the packaging perimeter is equal to or less than the chip naked chip length, or the packaging area is 1.5 times less than 1.5 times the area of the naked film. Therefore, the packaging efficiency of CSP (the ratio of the total area of the silicon wafer area to the packaging) is higher than that of QFP and BGA. CSP has some different structures, such as insertion types of deflection substrates, insertion types of ceramic rigid substrates, noodle array convex welded joints, and pins (1EAD on Chip). Such as LOC, it is different from the previous packaging structure. It no longer bonds the chip on the substrate first, and the surface is directly bonded on the pin frame (that is, cancel the substrate). (Can be reduced to 0.4mm ~ 0.5 mm).